`timescale 1ns / 1ps

module tb_dual_edge;
    reg clk;
    reg reset;
    reg level;
    wire tick1, tick2;
 
    // instantiate the design
    dual_edge_detector d1(.clk(clk), 
                          .reset(reset), 
                          .level(level), 
                          .tick1(tick1), .tick2(tick2));
 
    // initialize the clock
    initial clk = 1'b0;
 
    always #20 clk = ~clk;
 
    initial begin
        reset = 1'b1; level = 1'b0;
        #35 reset = 1'b0; level = 1'b0;
        #115 level = 1'b1;
        #90 level = 1'b0;
        #80 level = 1'b1;
        #90 level = 1'b0;
        #80 level = 1'b1;
        #100 level = 1'b0;
    end
 
endmodule